The present invention relates to integrated circuit devices and, more particularly, to integrated circuits that provide overvoltage protection.
Signal buffers are frequently coupled to input or input/output pads on an integrated circuit substrate so that external signals having voltage swings that are incompatible with the voltage levels used by devices on the integrated substrate can be level shifted and/or compressed to compatible levels. Hereinafter, input and input/output pads will be referred to as I/O pads. As illustrated by FIG. 1, a conventional CMOS input stage 100 may be used as a buffer for external signals received at an I/O pad 101. The CMOS input stage 100 may comprise a CMOS inverter 102 having an input connected to the I/O pad 101. As will be understood by those skilled in the art, the CMOS inverter 102 comprises a PMOS pull-up transistor 103 and an NMOS pull-down transistor 104. The output 105 of the CMOS inverter 102 is electrically connected to the drain of the NMOS pull-down transistor 104 and to the drain of the PMOS pull-up transistor 103, as illustrated. Because the PMOS pull-up transistor 103 and NMOS pull-down transistor 104 are connected in a totem pole arrangement between a positive power supply line and a ground reference potential, the voltage swing at the output 105 of the CMOS inverter 102 ranges from a minimum value of 0 Volts to a maximum value equal to the value of the positive power supply line Vdd.
Unfortunately, if an external signal received by the I/O pad 101 has an excessive positive voltage swing, the gate-to-drain voltage VGD across the PMOS pull-up transistor 103 and the gate-to-source voltage VGS and the gate-to-drain voltage VGD across the NMOS pull-down transistor 104 may exceed the ratings of these transistors and cause device breakdown. Moreover, even if the maximum voltage supplied by the external signal to the CMOS inverter 102 is not sufficient to cause breakdown, it may be high enough to cause degradation of the transfer characteristics of the CMOS inverter 102 if exposure to the high external signal is prolonged.
Attempts have been made to protect input buffers from external signals having excessive voltages. One such attempt is disclosed in U.S. Pat. No. 5,319,259 to Merrill, entitled xe2x80x9cLow Voltage Input and Output Circuits With Overvoltage Protectionxe2x80x9d. As illustrated by FIG. 2, which is a reproduction of FIG. 9 from the ""259 patent, an input stage 210 includes an input pad 200, a zener diode 201, an NMOS pass transistor 202, a supply terminal 203, a PMOS feedback transistor 204 and a CMOS inverter 205. The CMOS inverter 205 comprises an NMOS pull-down transistor 208 connected in a totem pole arrangement with a PMOS pull-up transistor 207. As illustrated, the PMOS feedback transistor 204 is electrically connected between an input 209 of the CMOS inverter 205 and the positive supply terminal 203. A gate of the PMOS feedback transistor 204 is electrically connected to an output 206 of the CMOS inverter 205.
As will be understood by those skilled in the art, the zener diode 201 provides overvoltage protection for external signals having voltages in excess of about six (6) Volts. However, the NMOS pass transistor 202 provides overvoltage protection for external signals having voltages in a range between about six (6) Volts and the magnitude of the power supply voltage Vdd applied to the supply terminal 203. For example, if an external signal having a voltage of 5 Volts is applied to the input pad 200 and the operating supply voltage is 2.5 Volts, the NMOS pass transistor 202 will initially reduce the 5 Volt signal level to an input node 209 at the input 209 that is equal to Vddxe2x88x92VTH-pass, where VTH-pass is the threshold voltage of the NMOS pass transistor 202, perhaps 0.5 Volts. The voltage V209 at the input of the CMOS inverter 205 is sufficient to cause the output 206 of the CMOS inverter 205 to be pulled down to a logic 0 level. As illustrated, the logic 0 signal at the output 206 is fed back to the PMOS feedback transistor 204, which then turns on to pull input node 209 up to the full supply voltage Vdd.
The PMOS feedback transistor 204 should be designed to have relatively weak pull-up characteristics so that an external signal transitioning from a logic 1 level to a logic 0 level will be able to overcome the pull-up logic force provided by the PMOS feedback transistor 204. The PMOS feedback transistor 204 may be made relatively weak by making its channel relatively long or relatively narrow. Unfortunately, when an external signal transitions from a logic 1 level to a logic 0 level, the NMOS pass transistor 202 and the PMOS feedback transistor 204 initially operate as a pair of resistors connected in series between the input pad 200 and the supply terminal 203. This series resistive path to Vdd slows the pull-down transition. More significantly, the series resistive path prevents the input from meeting a typical input specification of nominally zero current, which presents a marketing problem for a product using this circuit.
Thus, notwithstanding these attempts to provide signal buffers that are capable of compressing external signal levels to internal voltages that are compatible with on-chip circuitry, there continues to be a need for signal buffers that occupy low area, have low power consumption requirements and limit all gate-to-source, gate-to-drain and drain-to-source voltages to safe voltages for the transistors contained therein.
Overvoltage protection circuits according to embodiments of the present invention protect devices connected thereto by clamping input signals having excessive positive voltages in an efficient manner that does not damage either the overvoltage protection circuit itself or the other circuits connected thereto. One preferred overvoltage protection circuit includes a first NMOS pass transistor connected between an input signal line (IN) and an output signal line (OUT) to which an input of a load or logic device (e.g., inverter, multi-input logic gate) is connected. A gate of the first pass transistor is preferably connected to a signal line upon which a variable positive voltage level is maintained.
When an input signal (Vin) having a logic 0 level (low voltage) is provided to the input signal line IN, the first pass transistor operates as a normally-on transistor that passes the input signal Vin directly to the output signal line OUT. However, as the input signal Vin transitions from a logic 0 level to a voltage level above a supply voltage Vdd during a pull-up interval, the first pass transistor transitions from a highly conductive on-state to an off-state. In particular, the first pass transistor transitions to an off-state when a positive voltage on the output signal line OUT equals Vgatexe2x88x92Vth, where Vgate is the gate voltage of the first pass transistor and Vth is a threshold voltage of the first pass transistor. At this point, the first pass transistor blocks further increases in the magnitude of the input signal Vin from being passed to the output signal line OUT. By action of the first pass transistor, the output signal line OUT is thereby clamped at a maximum level of Vgatexe2x88x92Vth, with further increases in Vin appearing across the drain and source terminals of the first pass transistor.
To prevent clamping of the output signal line OUT at a positive voltage below Vdd, it is advantageous to provide a gate voltage of the first pass transistor above Vdd, because the source voltage can follow the drain voltage only to the gate voltage less the threshold voltage of the first pass transistor. To achieve this goal, the gate of the first pass transistor is connected to a circuit that clamps the gate of the first pass transistor within a range of voltages. This range of gate voltages extends from a minimum clamped level to a maximum clamped level. In particular, a width of the first pass transistor is set at a relatively high level so that significant capacitive coupling (i.e., gate-to-channel capacitance) is provided between the signal lines IN and OUT and the gate of the first pass transistor. Thus, as the magnitude of the input signal Vin increases, the magnitude of the voltage at the gate of the first pass transistor increases in a self-bootstapping manner, within the range permitted by the clamping circuit.
The clamping circuit preferably clamps the voltage at the gate of the first pass transistor at a maximum level that enables the output signal line OUT to reach a maximum level of about Vdd. To achieve this preferred maximum logic 1 voltage on the output signal line OUT, the clamping circuit preferably clamps the gate of the first pass transistor at a maximum voltage of about Vdd+xcex1, where a is preferably equal to Vth, and Vth equals a threshold voltage of the first pass transistor. As will be discussed in detail below, this first transistor will pass input voltages that are below or equal to Vdd to the output signal line OUT, but will not pass voltages above Vdd to the output signal line OUT.
According to a preferred aspect of this embodiment, the clamping circuit comprises first and second diodes electrically connected in antiparallel between a second power supply line and a gate of the first pass transistor. These first and second diodes operate to clamp the voltage appearing at the gate of the first pass transistor to within a desired range of voltages. These first and second diodes may comprise first and second NMOS transistors, respectively. According to a preferred aspect of this embodiment, a source of the first NMOS transistor, which operates as a cathode of the first diode, is electrically connected to a drain and gate of the second NMOS transistor and to the gate of the first pass transistor. The drain and gate of the second NMOS transistor operate as an anode of the second diode. A source of the second NMOS transistor is electrically connected to a drain and gate of the first NMOS transistor and to the second power supply line. According to an additional preferred aspect of this embodiment, a width of the first pass transistor is relatively large relative to the widths of the first and second NMOS transistors operating as diodes to thereby provide a high degree of capacitive coupling between the input and output signal lines and the gate of the first pass transistor. This high degree of capacitive coupling causes the voltage on the gate of the first pass transistor to immediately rise above the minimum clamped level as the input signal commences a transition from a logic 0 level to a logic 1 level.
According to a second embodiment of the present invention, an overvoltage protection circuit is provided that comprises first and second pass transistors electrically connected in parallel between an input signal line (IN) and an output signal line (OUT). A first power supply line is electrically coupled to a gate of the second pass transistor so that the gate of the second pass transistor is held at a fixed high voltage (e.g., Vdd). This second pass transistor improves the pull-down speed of the overvoltage protection circuit by turning on before the first pass transistor when the input signal line IN is switching from a high positive voltage to a logic 0 level during a pull-down interval. A voltage clamping circuit is also provided. This voltage clamping circuit is similar to the clamping circuit described above with respect to the first embodiment, however, the first and second diodes are electrically connected in antiparallel between a second power supply line and a gate of the first pass transistor. The first and second power supply lines may be electrically connected together so that the magnitude of the supply voltages is the same.
The clamping circuit clamps a voltage at the gate of the first pass transistor at a minimum voltage of about Vdd2xe2x88x92VTN1 in response to application of a logic 0 input signal Vin, where VTN1 is a threshold voltage of the first NMOS transistor. The gate of the first pass transistor is also clamped at a maximum voltage of Vdd2+VTN2 in response to a positive transition of an input signal Vin by an amount equal to about VTN1+VTN2 (the exact amount depends on the ratio of the channel capacitance of the first pass transistor relative to the combined capacitance of the first and second diodes within the clamping circuit).
According to a third embodiment of the present invention, a signal buffer comprises a first pass transistor electrically connected between an input signal line and an output signal line. A preferred clamping circuit is provided to dynamically clamp a voltage at a gate of the first pass transistor. In particular, the clamping circuit dynamically clamps a voltage at the gate of the first pass transistor to within a first range so that a full logic 1 voltage (e.g., Vdd1 but no more) can be established on the output signal line and magnitudes of all gate-to-source, gate-to-drain and drain-to-source voltages across any transistor will not exceed a level in excess of Vdd, even when Vin is raised to a level as high as 2Vdd.